pub enum SuperHInstruction {
Show 235 variants MovImm(u8SuperHRegister), MovImmW(Displacement8SuperHRegister), MovImmL(Displacement8SuperHRegister), MovReg(SuperHRegisterSuperHRegister), MovToAtRegB(SuperHRegisterSuperHRegister), MovToAtRegW(SuperHRegisterSuperHRegister), MovToAtRegL(SuperHRegisterSuperHRegister), MovFromAtRegB(SuperHRegisterSuperHRegister), MovFromAtRegW(SuperHRegisterSuperHRegister), MovFromAtRegL(SuperHRegisterSuperHRegister), MovToAtRegPreDecrementB(SuperHRegisterSuperHRegister), MovToAtRegPreDecrementW(SuperHRegisterSuperHRegister), MovToAtRegPreDecrementL(SuperHRegisterSuperHRegister), MovFromAtRegPostIncrementB(SuperHRegisterSuperHRegister), MovFromAtRegPostIncrementW(SuperHRegisterSuperHRegister), MovFromAtRegPostIncrementL(SuperHRegisterSuperHRegister), MovToAtDisplacedRegisterB(Displacement4SuperHRegister), MovToAtDisplacedRegisterW(Displacement4SuperHRegister), MovToAtDisplacedRegisterL(SuperHRegisterDisplacement4SuperHRegister), MovFromAtDisplacedRegisterB(Displacement4SuperHRegister), MovFromAtDisplacedRegisterW(Displacement4SuperHRegister), MovFromAtDisplacedRegisterL(Displacement4SuperHRegisterSuperHRegister), MovToAtIndexedRegisterB(SuperHRegisterSuperHRegister), MovToAtIndexedRegisterW(SuperHRegisterSuperHRegister), MovToAtIndexedRegisterL(SuperHRegisterSuperHRegister), MovFromAtIndexedRegisterB(SuperHRegisterSuperHRegister), MovFromAtIndexedRegisterW(SuperHRegisterSuperHRegister), MovFromAtIndexedRegisterL(SuperHRegisterSuperHRegister), MovToAtDisplacedGbrB(Displacement8), MovToAtDisplacedGbrW(Displacement8), MovToAtDisplacedGbrL(Displacement8), MovFromAtDisplacedGbrB(Displacement8), MovFromAtDisplacedGbrW(Displacement8), MovFromAtDisplacedGbrL(Displacement8), Mova(Displacement8), Movt(SuperHRegister), SwapB(SuperHRegisterSuperHRegister), SwapW(SuperHRegisterSuperHRegister), Xtrct(SuperHRegisterSuperHRegister), AddReg(SuperHRegisterSuperHRegister), AddImm(u8SuperHRegister), AddC(SuperHRegisterSuperHRegister), AddV(SuperHRegisterSuperHRegister), CmpEqImm(u8), CmpEqReg(SuperHRegisterSuperHRegister), CmpHs(SuperHRegisterSuperHRegister), CmpGe(SuperHRegisterSuperHRegister), CmpHi(SuperHRegisterSuperHRegister), CmpGt(SuperHRegisterSuperHRegister), CmpPz(SuperHRegister), CmpPl(SuperHRegister), CmpStr(SuperHRegisterSuperHRegister), Div1(SuperHRegisterSuperHRegister), Div0S(SuperHRegisterSuperHRegister), Div0U, DmulsL(SuperHRegisterSuperHRegister), DmuluL(SuperHRegisterSuperHRegister), Dt(SuperHRegister), ExtsB(SuperHRegisterSuperHRegister), ExtsW(SuperHRegisterSuperHRegister), ExtuB(SuperHRegisterSuperHRegister), ExtuW(SuperHRegisterSuperHRegister), MacL(SuperHRegisterSuperHRegister), MacW(SuperHRegisterSuperHRegister), MulL(SuperHRegisterSuperHRegister), MulsW(SuperHRegisterSuperHRegister), MuluW(SuperHRegisterSuperHRegister), Neg(SuperHRegisterSuperHRegister), Negc(SuperHRegisterSuperHRegister), Sub(SuperHRegisterSuperHRegister), Subc(SuperHRegisterSuperHRegister), Subv(SuperHRegisterSuperHRegister), AndReg(SuperHRegisterSuperHRegister), AndImm(u8), AndB(u8), Not(SuperHRegisterSuperHRegister), OrReg(SuperHRegisterSuperHRegister), OrImm(u8), OrB(u8), TasB(SuperHRegister), TstReg(SuperHRegisterSuperHRegister), TstImm(u8), TstB(u8), XorReg(SuperHRegisterSuperHRegister), XorImm(u8), XorB(u8), RotL(SuperHRegister), RotR(SuperHRegister), RotcL(SuperHRegister), RotcR(SuperHRegister), ShaD(SuperHRegisterSuperHRegister), ShaL(SuperHRegister), ShaR(SuperHRegister), ShlD(SuperHRegisterSuperHRegister), ShlL(SuperHRegister), ShlR(SuperHRegister), ShlL2(SuperHRegister), ShlR2(SuperHRegister), ShlL8(SuperHRegister), ShlR8(SuperHRegister), ShlL16(SuperHRegister), ShlR16(SuperHRegister), Bf(Displacement8), BfS(Displacement8), Bt(Displacement8), BtS(Displacement8), Bra(Displacement12), BraF(SuperHRegister), Bsr(Displacement12), BsrF(SuperHRegister), Jmp(SuperHRegister), Jsr(SuperHRegister), Rts, ClrMac, ClrS, ClrT, LdcSr(SuperHRegister), LdcGbr(SuperHRegister), LdcVbr(SuperHRegister), LdcSsr(SuperHRegister), LdcSpc(SuperHRegister), LdcDbr(SuperHRegister), LdcRnBank(SuperHRegisterSuperHRegisterBank), LdcLSr(SuperHRegister), LdcLGbr(SuperHRegister), LdcLVbr(SuperHRegister), LdcLSsr(SuperHRegister), LdcLSpc(SuperHRegister), LdcLDbr(SuperHRegister), LdcLRnBank(SuperHRegisterSuperHRegisterBank), LdsMach(SuperHRegister), LdsMacl(SuperHRegister), LdsPr(SuperHRegister), LdsLMach(SuperHRegister), LdsLMacl(SuperHRegister), LdsLPr(SuperHRegister), Ldtlb, MovcaL(SuperHRegister), Nop, OcbI(SuperHRegister), OcbP(SuperHRegister), OcbWb(SuperHRegister), Pref(SuperHRegister), Rte, SetS, SetT, Sleep, StcSr(SuperHRegister), StcGbr(SuperHRegister), StcVbr(SuperHRegister), StcSsr(SuperHRegister), StcSpc(SuperHRegister), StcSgr(SuperHRegister), StcDbr(SuperHRegister), StcRmBank(SuperHRegisterBankSuperHRegister), StcLSr(SuperHRegister), StcLGbr(SuperHRegister), StcLVbr(SuperHRegister), StcLSsr(SuperHRegister), StcLSpc(SuperHRegister), StcLSgr(SuperHRegister), StcLDbr(SuperHRegister), StcLRmBank(SuperHRegisterBankSuperHRegister), StsMach(SuperHRegister), StsMacl(SuperHRegister), StsPr(SuperHRegister), StsLMach(SuperHRegister), StsLMacl(SuperHRegister), StsLPr(SuperHRegister), Trapa(u8), Fldi0(SuperHFloatRegister), Fldi1(SuperHFloatRegister), FMovS(SuperHFloatRegisterSuperHFloatRegister), FMovAtRegS(SuperHRegisterSuperHFloatRegister), FMovAtIndexedRegisterS(SuperHRegisterSuperHFloatRegister), FMovAtPostIncrementRegS(SuperHRegisterSuperHFloatRegister), FMovToAtRegS(SuperHFloatRegisterSuperHRegister), FMovToAtPreDecrementRegS(SuperHFloatRegisterSuperHRegister), FMovToAtIndexedRegisterS(SuperHFloatRegisterSuperHRegister), FMov(SuperHDoubleRegisterSuperHDoubleRegister), FMovAtReg(SuperHRegisterSuperHDoubleRegister), FMovAtIndexedRegister(SuperHRegisterSuperHDoubleRegister), FMovAtPostIncrementReg(SuperHRegisterSuperHDoubleRegister), FMovToAtReg(SuperHDoubleRegisterSuperHRegister), FMovToAtPreDecrementReg(SuperHDoubleRegisterSuperHRegister), FMovToAtIndexedRegister(SuperHDoubleRegisterSuperHRegister), Flds(SuperHFloatRegister), Fsts(SuperHFloatRegister), FabsS(SuperHFloatRegister), FaddS(SuperHFloatRegisterSuperHFloatRegister), FcmpEqS(SuperHFloatRegisterSuperHFloatRegister), FcmpGtS(SuperHFloatRegisterSuperHFloatRegister), FdivS(SuperHFloatRegisterSuperHFloatRegister), FloatS(SuperHFloatRegister), Fmac(SuperHFloatRegisterSuperHFloatRegister), FmulS(SuperHFloatRegisterSuperHFloatRegister), FnegS(SuperHFloatRegister), FsqrtS(SuperHFloatRegister), FsubS(SuperHFloatRegisterSuperHFloatRegister), FrtcS(SuperHFloatRegister), Fabs(SuperHDoubleRegister), Fadd(SuperHDoubleRegisterSuperHDoubleRegister), FcmpEq(SuperHDoubleRegisterSuperHDoubleRegister), FcmpGt(SuperHDoubleRegisterSuperHDoubleRegister), Fdiv(SuperHDoubleRegisterSuperHDoubleRegister), FcnvDs(SuperHDoubleRegister), FcnvSd(SuperHDoubleRegister), Float(SuperHDoubleRegister), Fmul(SuperHDoubleRegisterSuperHDoubleRegister), Fneg(SuperHDoubleRegister), Fsqrt(SuperHDoubleRegister), Fsub(SuperHDoubleRegisterSuperHDoubleRegister), Frtc(SuperHDoubleRegister), LdsFpscr(SuperHRegister), LdsFpul(SuperHRegister), LdsFpscrL(SuperHRegister), LdsFpulL(SuperHRegister), StsFpscr(SuperHRegister), StsFpul(SuperHRegister), StsFpscrL(SuperHRegister), StsFpulL(SuperHRegister), FMovToX(SuperHDoubleRegisterSuperHExtendedDoubleRegister), FMovFromX(SuperHExtendedDoubleRegisterSuperHDoubleRegister), FMovX(SuperHExtendedDoubleRegisterSuperHExtendedDoubleRegister), FMovAtRegX(SuperHRegisterSuperHExtendedDoubleRegister), FMovAtPostIncrementRegX(SuperHRegisterSuperHExtendedDoubleRegister), FMovAtIndexedRegisterX(SuperHRegisterSuperHExtendedDoubleRegister), FMovToAtRegX(SuperHExtendedDoubleRegisterSuperHRegister), FMovToAtPreDecrementRegX(SuperHExtendedDoubleRegisterSuperHRegister), FMovToAtIndexedRegisterX(SuperHExtendedDoubleRegisterSuperHRegister), Fipr(SuperHVectorFloatRegisterSuperHVectorFloatRegister), Xmrtx(SuperHVectorFloatRegister), FrChg, FsChg, CasL(SuperHRegisterSuperHRegister),
}

Variants

MovImm(u8SuperHRegister)

MOV #imm,Rn (imm → sign extension → Rn) 1110nnnniiiiiiii

MovImmW(Displacement8SuperHRegister)

MOV.W @(disp,PC),Rn ((disp * 2 + PC + 4) → sign extension → Rn) 1001nnnndddddddd

MovImmL(Displacement8SuperHRegister)

MOV.L @(disp,PC),Rn ((disp * 2 + PC & 0xFFFF_FFFC + 4)Rn) 1101nnnndddddddd

MovReg(SuperHRegisterSuperHRegister)

MOV Rm,Rn (RmRn) 0110nnnnmmmm0011

MovToAtRegB(SuperHRegisterSuperHRegister)

MOV.B Rm,@Rn (Rm → sign extension → (Rn)) 0010nnnnmmmm0000

MovToAtRegW(SuperHRegisterSuperHRegister)

MOV.W Rm,@Rn (Rm → sign extension → (Rn)) 0010nnnnmmmm0001

MovToAtRegL(SuperHRegisterSuperHRegister)

MOV.L Rm,@Rn (Rm(Rn)) 0010nnnnmmmm0010

MovFromAtRegB(SuperHRegisterSuperHRegister)

MOV.B @Rm,Rn ((Rm) → sign extension → Rn) 0110nnnnmmmm0000

MovFromAtRegW(SuperHRegisterSuperHRegister)

MOV.W @Rm,Rn ((Rm) → sign extension → Rn) 0110nnnnmmmm0001

MovFromAtRegL(SuperHRegisterSuperHRegister)

MOV.L @Rm,Rn ((Rm)Rn) 0110nnnnmmmm0010

MovToAtRegPreDecrementB(SuperHRegisterSuperHRegister)

MOV.B Rm,@-Rn (Rn - 1Rn, Rm(Rn)) 0010nnnnmmmm0100

MovToAtRegPreDecrementW(SuperHRegisterSuperHRegister)

MOV.W Rm,@-Rn (Rn - 2Rn, Rm(Rn)) 0010nnnnmmmm0101

MovToAtRegPreDecrementL(SuperHRegisterSuperHRegister)

MOV.L Rm,@-Rn (Rn - 4Rn, Rm(Rn)) 0010nnnnmmmm0110

MovFromAtRegPostIncrementB(SuperHRegisterSuperHRegister)

MOV.B @Rm+,Rn ((Rm) → sign extension → Rn, Rm + 1Rm) 0110nnnnmmmm0100

MovFromAtRegPostIncrementW(SuperHRegisterSuperHRegister)

MOV.W @Rm+,Rn ((Rm) → sign extension → Rn, Rm + 2Rm) 0110nnnnmmmm0101

MovFromAtRegPostIncrementL(SuperHRegisterSuperHRegister)

MOV.L @Rm+,Rn ((Rm) → sign extension → Rn, Rm + 4Rm) 0110nnnnmmmm0110

MovToAtDisplacedRegisterB(Displacement4SuperHRegister)

MOV.B R0,@(disp,Rn) (R0(disp + Rn)) 10000000nnnndddd

MovToAtDisplacedRegisterW(Displacement4SuperHRegister)

MOV.W R0,@(disp,Rn) (R0(disp * 2 + Rn)) 10000001nnnndddd

MovToAtDisplacedRegisterL(SuperHRegisterDisplacement4SuperHRegister)

MOV.L Rm,@(disp,Rn) (Rm(disp * 4 + Rn)) 0001nnnnmmmmdddd

MovFromAtDisplacedRegisterB(Displacement4SuperHRegister)

MOV.B @(disp,Rm),R0 ((disp + Rm) → sign extension → R0) 10000100mmmmdddd

MovFromAtDisplacedRegisterW(Displacement4SuperHRegister)

MOV.W @(disp,Rm),R0 ((disp * 2 + Rm) → sign extension → R0) 10000101mmmmdddd

MovFromAtDisplacedRegisterL(Displacement4SuperHRegisterSuperHRegister)

MOV.L @(disp,Rm),Rn ((disp * 4 + Rm)Rn) 0101nnnnmmmmdddd

MovToAtIndexedRegisterB(SuperHRegisterSuperHRegister)

MOV.B Rm,@(R0,Rn) (Rm(R0 + Rn)) 0000nnnnmmmm0100

MovToAtIndexedRegisterW(SuperHRegisterSuperHRegister)

MOV.W Rm,@(R0,Rn) (Rm(R0 + Rn)) 0000nnnnmmmm0101

MovToAtIndexedRegisterL(SuperHRegisterSuperHRegister)

MOV.L Rm,@(R0,Rn) (Rm(R0 + Rn)) 0000nnnnmmmm0110

MovFromAtIndexedRegisterB(SuperHRegisterSuperHRegister)

MOV.B @(R0,Rm),Rn ((R0 + Rm) → sign extension → Rn) 0000nnnnmmmm1100

MovFromAtIndexedRegisterW(SuperHRegisterSuperHRegister)

MOV.W @(R0,Rm),Rn ((R0 + Rm) → sign extension → Rn) 0000nnnnmmmm1101

MovFromAtIndexedRegisterL(SuperHRegisterSuperHRegister)

MOV.L @(R0,Rm),Rn ((R0 + Rm)Rn) 0000nnnnmmmm1110

MovToAtDisplacedGbrB(Displacement8)

MOV.B R0,@(disp,GBR) (R0(disp + GBR)) 11000000dddddddd

MovToAtDisplacedGbrW(Displacement8)

MOV.W R0,@(disp,GBR) (R0(disp * 2 + GBR)) 11000001dddddddd

MovToAtDisplacedGbrL(Displacement8)

MOV.L R0,@(disp,GBR) (R0(disp * 4 + GBR)) 11000010dddddddd

MovFromAtDisplacedGbrB(Displacement8)

MOV.B @(disp,GBR),R0 ((disp + GBR) → sign extension → R0) 11000100dddddddd

MovFromAtDisplacedGbrW(Displacement8)

MOV.W @(disp,GBR),R0 ((disp * 2 + GBR) → sign extension → R0) 11000101dddddddd

MovFromAtDisplacedGbrL(Displacement8)

MOV.L @(disp,GBR),R0 ((disp * 4 + GBR)R0) 11000110dddddddd

Mova(Displacement8)

MOVA @(disp,PC),R0 (disp * 4 + PC & 0xFFFF_FFFC + 4R0) 11000111dddddddd

Movt(SuperHRegister)

MOVT Rn (TRn) 0000nnnn00101001

SwapB(SuperHRegisterSuperHRegister)

SWAP.B Rm,Rn (Rm → swap lower 2 bytes → REG) 0110nnnnmmmm1000

SwapW(SuperHRegisterSuperHRegister)

SWAP.W Rm,Rn (Rm → swap upper/lower words → REG) 0110nnnnmmmm1001

Xtrct(SuperHRegisterSuperHRegister)

XTRCT Rm,Rn (Rm:Rn middle 32 bits → Rn) 0010nnnnmmmm1101

AddReg(SuperHRegisterSuperHRegister)

ADD Rm,Rn (Rn + RmRn) 0011nnnnmmmm1100

AddImm(u8SuperHRegister)

ADD #imm,Rn (Rn + immRn) 0111nnnniiiiiiii

AddC(SuperHRegisterSuperHRegister)

ADDC Rm,Rn (Rn + Rm + TRn, carry → T) 0011nnnnmmmm1110 T = Carry

AddV(SuperHRegisterSuperHRegister)

ADDV Rm,Rn (Rn + RmRn, overflow → T) 0011nnnnmmmm1111 T = Overflow

CmpEqImm(u8)

CMP/EQ #imm,R0 (When R0 = imm, 1 → T; Otherwise, 0 → T) 10001000iiiiiiii T = Comparison result

CmpEqReg(SuperHRegisterSuperHRegister)

CMP/EQ Rm,Rn (When Rn = Rm, 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0000 T = Comparison result

CmpHs(SuperHRegisterSuperHRegister)

CMP/HS Rm,Rn (When RnRm (unsigned), 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0010 T = Comparison result

CmpGe(SuperHRegisterSuperHRegister)

CMP/GE Rm,Rn (When RnRm (signed), 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0011 T = Comparison result

CmpHi(SuperHRegisterSuperHRegister)

CMP/HI Rm,Rn (When Rn > Rm (unsigned), 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0110 T = Comparison result

CmpGt(SuperHRegisterSuperHRegister)

CMP/GT Rm,Rn (When Rn > Rm (signed), 1 → T; Otherwise, 0 → T) 0011nnnnmmmm0111 T = Comparison result

CmpPz(SuperHRegister)

CMP/PZ Rn (When Rn ≥ 0, 1 → T; Otherwise, 0 → T) 0100nnnn00010001 T = Comparison result

CmpPl(SuperHRegister)

CMP/PL Rn (When Rn > 0, 1 → T; Otherwise, 0 → T) 0100nnnn00010101 T = Comparison result

CmpStr(SuperHRegisterSuperHRegister)

CMP/STR Rm,Rn (When any bytes are equal, 1 → T; Otherwise, 0 → T) 0010nnnnmmmm1100 T = Comparison result

Div1(SuperHRegisterSuperHRegister)

DIV1 Rm,Rn (1-step division (Rn ÷ Rm)) 0011nnnnmmmm0100 T = Calculation result

Div0S(SuperHRegisterSuperHRegister)

DIV0S Rm,Rn (MSB of RnQ, MSB of RmM, M ^ QT) 0010nnnnmmmm0111 T = Calculation result

Div0U

DIV0U (0 → M/Q/T) 0000000000011001 T = 0

DmulsL(SuperHRegisterSuperHRegister)

DMULS.L Rm,Rn (Signed, Rn * RmMAC, 32 * 32 → 64 bits) 0011nnnnmmmm1101

Level: Sh2

DmuluL(SuperHRegisterSuperHRegister)

DMULU.L Rm,Rn (Unsigned, Rn * RmMAC, 32 * 32 → 64 bits) 0011nnnnmmmm0101

Level: Sh2

Dt(SuperHRegister)

DT Rn (Rn - 1Rn; When Rn = 0, 1 → T; Otherwise Rn ≠ 0, 0 → T) 0100nnnn00010000 T = Comparison result

Level: Sh2

ExtsB(SuperHRegisterSuperHRegister)

EXTS.B Rm,Rn (Rm sign-extended from byte → Rn) 0110nnnnmmmm1110

ExtsW(SuperHRegisterSuperHRegister)

EXTS.W Rm,Rn (Rm sign-extended from word → Rn) 0110nnnnmmmm1111

ExtuB(SuperHRegisterSuperHRegister)

EXTU.B Rm,Rn (Rm zero-extended from byte → Rn) 0110nnnnmmmm1100

ExtuW(SuperHRegisterSuperHRegister)

EXTU.W Rm,Rn (Rm zero-extended from word → Rn) 0110nnnnmmmm1101

MacL(SuperHRegisterSuperHRegister)

MAC.L @Rm+,@Rn+ (Signed, (Rn) * (Rm) + MACMAC, Rn + 4Rn, Rm + 4 → Rm; 32 * 32 + 64 → 64 bits) 0000nnnnmmmm1111`

Level: Sh2

MacW(SuperHRegisterSuperHRegister)

MAC.L @Rm+,@Rn+ (Signed, (Rn) * (Rm) + MACMAC, Rn + 2Rn, Rm + 2 → Rm; 16 * 16 + 64 → 64 bits) 0100nnnnmmmm1111`

MulL(SuperHRegisterSuperHRegister)

MAC.L Rm,Rn (Rn * RmMACL, 32 * 32→ 32 bits) 0000nnnnmmmm0111

Level: Sh2

MulsW(SuperHRegisterSuperHRegister)

MULS.W Rm,Rn (Signed, Rn * RmMACL, 16 * 16 → 32 bits) 0010nnnnmmmm1111

MuluW(SuperHRegisterSuperHRegister)

MULU.W Rm,Rn (Unsigned, Rn * RmMACL, 16 * 16 → 32 bits) 0010nnnnmmmm1110

Neg(SuperHRegisterSuperHRegister)

NEG Rm,Rn (0 - Rm → Rn) 0110nnnnmmmm1011

Negc(SuperHRegisterSuperHRegister)

NEGC Rm,Rn (0 - Rm - TRn, borrow → T) 0110nnnnmmmm1010 T = Borrow

Sub(SuperHRegisterSuperHRegister)

SUB Rm,Rn (Rn - Rm → Rn) 0011nnnnmmmm1000

Subc(SuperHRegisterSuperHRegister)

SUBC Rm,Rn (Rn - Rm - TRn, borrow → T) 0011nnnnmmmm1010 T = Borrow

Subv(SuperHRegisterSuperHRegister)

SUBV Rm,Rn (Rn - RmRn, underflow → T) 0011nnnnmmmm1011 T = Underflow

AndReg(SuperHRegisterSuperHRegister)

AND Rm,Rn (Rn & RmRn) 0010nnnnmmmm1001

AndImm(u8)

AND #imm,R0 (R0 & immR0) 11001001iiiiiiii

AndB(u8)

AND.B #imm,@(R0,GBR) ((R0 + GBR) & imm(R0 + GBR)) 11001101iiiiiiii

Not(SuperHRegisterSuperHRegister)

NOT Rm,Rn (~RmRn) 0110nnnnmmmm0111

OrReg(SuperHRegisterSuperHRegister)

OR Rm,Rn (Rn | RmRn) 0010nnnnmmmm1011

OrImm(u8)

OR #imm,R0 (R0 | immR0) 11001011iiiiiiii

OrB(u8)

OR.B #imm,@(R0,GBR) ((R0 + GBR) | imm(R0 + GBR)) 11001111iiiiiiii

TasB(SuperHRegister)

TAS.B @Rn (When (Rn) = 0, 1 → T; Otherwise, 0 → T; In both cases, 1 → MSB of (Rn)) 0100nnnn00011011 T = Test result

TstReg(SuperHRegisterSuperHRegister)

TST Rm,Rn (Rn & Rm; when result = 0, 1 → T; Otherwise, 0 → T) 0010nnnnmmmm1000 T = Test result

TstImm(u8)

TST #imm,R0 (R0 & imm; when result = 0, 1 → T; Otherwise, 0 → T) 11001000iiiiiiii T = Test result

TstB(u8)

TST.B #imm,@(R0,GBR) ((R0 + GBR) & imm, When result = 0, 1 → T; Otherwise, 0 → T) 11001100iiiiiiii T = Test result

XorReg(SuperHRegisterSuperHRegister)

XOR Rm,Rn (Rn ^ Rm → Rn) 0010nnnnmmmm1010 T = Test result

XorImm(u8)

XOR #imm,R0 (R0 ^ imm → R0) 11001010iiiiiiii T = Test result

XorB(u8)

XOR.B #imm,@(R0,GBR) ((R0 + GBR) ^ imm → R0) 11001110iiiiiiii T = Test result

RotL(SuperHRegister)

ROTL Rn (TRnMSB) 0100nnnn00000100 T = MSB

RotR(SuperHRegister)

ROTR Rn (LSBRnT) 0100nnnn00000101 T = LSB

RotcL(SuperHRegister)

ROTCL Rn (TRnT) 0100nnnn00100100 T = MSB

RotcR(SuperHRegister)

ROTCR Rn (TRnT) 0100nnnn00100101 T = LSB

ShaD(SuperHRegisterSuperHRegister)

SHAD Rm,Rn (When Rn ≥ 0, Rn << RmRn, When Rn < 0, Rn >> Rm → [MSBRn]) 0100nnnnmmmm1100

Level: J2

ShaL(SuperHRegister)

SHAL Rn (TRn ← 0) 0100nnnn00100000 T = MSB

ShaR(SuperHRegister)

SHAR Rn (MSB → RnT) 0100nnnn00100001 T = LSB

ShlD(SuperHRegisterSuperHRegister)

SHLD Rm,Rn (When Rn ≥ 0, Rn << RmRn, When Rn < 0, Rn >> Rm → [0Rn]) 0100nnnnmmmm1101

Level: J2

ShlL(SuperHRegister)

SHLL Rn (TRn ← 0) 0100nnnn00000000 T = MSB

ShlR(SuperHRegister)

SHLR Rn (0 → RnT) 0100nnnn00000001 T = LSB

ShlL2(SuperHRegister)

SHLL2 Rn (Rn << 2Rn) 0100nnnn00001000

ShlR2(SuperHRegister)

SHLR2 Rn (Rn >> 2Rn) 0100nnnn00001001

ShlL8(SuperHRegister)

SHLL8 Rn (Rn << 8Rn) 0100nnnn00011000

ShlR8(SuperHRegister)

SHLR8 Rn (Rn >> 8Rn) 0100nnnn00011001

ShlL16(SuperHRegister)

SHLL16 Rn (Rn << 16Rn) 0100nnnn00101000

ShlR16(SuperHRegister)

SHLR16 Rn (Rn >> 16Rn) 0100nnnn00101001

Bf(Displacement8)

BF label (When T = 0, disp * 2 + PC + 4PC, When T = 1, nop) 10001011dddddddd

BfS(Displacement8)

BF/S label (Delayed branch; When T = 0, disp * 2 + PC + 4PC, When T = 1, nop) 10001111dddddddd

Level: Sh2

Bt(Displacement8)

BT label (When T = 1, disp * 2 + PC + 4PC, When T = 0, nop) 10001001dddddddd

BtS(Displacement8)

BT/S label (Delayed branch; When T = 1, disp * 2 + PC + 4PC, When T = 0, nop) 10001101dddddddd

Level: Sh2

Bra(Displacement12)

BRA label (Delayed branch; disp * 2 + PC + 4PC) 1010dddddddddddd

BraF(SuperHRegister)

BRA Rn (Delayed branch; Rn + PC + 4PC) 0000nnnn00100011

Level: Sh2

Bsr(Displacement12)

BSR label (Delayed branch; PC + 4PR, disp * 2 + PC + 4PC) 1011dddddddddddd

BsrF(SuperHRegister)

BSR Rn (Delayed branch; PC + 4PR, Rn + PC + 4PC) 0000nnnn00000011

Level: Sh2

Jmp(SuperHRegister)

JMP @Rn (Delayed branch; RnPC) 0100nnnn00101011

Jsr(SuperHRegister)

JSR @Rn (Delayed branch; PC + 4PR, RnPC) 0100nnnn00001011

Rts

RTS (Delayed branch; PRPC) 0000000000001011

ClrMac

CLRMAC (0 → MACH, MACL) 0000000000101000

ClrS

CLRS (0 → S) 0000000001001000

Level: Sh3

ClrT

CLRT (0 → T) 0000000000001000 T = 0

LdcSr(SuperHRegister)

LDC Rm,SR (RmSR) 0100mmmm00001110 T = LSB

Privileged

LdcGbr(SuperHRegister)

LDC Rm,GBR (RmGBR) 0100mmmm00011110

LdcVbr(SuperHRegister)

LDC Rm,VBR (RmVBR) 0100mmmm00101110

Privileged

LdcSsr(SuperHRegister)

LDC Rm,SSR (RmSSR) 0100mmmm00111110

Privileged Level: Sh3

LdcSpc(SuperHRegister)

LDC Rm,SPC (RmSPC) 0100mmmm01001110

Privileged Level: Sh3

LdcDbr(SuperHRegister)

LDC Rm,DBR (RmDBR) 0100mmmm11111010

Privileged Level: Sh4

LdcRnBank(SuperHRegisterSuperHRegisterBank)

LDC Rm,Rn_BANK (RmRn_BANK (n = 0 to 7)) 0100mmmm1nnn1110

Privileged Level: Sh3

LdcLSr(SuperHRegister)

LDC.L @Rm+,SR ((Rm)SR, Rm + 4Rm) 0100mmmm00000111 T = LSB

Privileged

LdcLGbr(SuperHRegister)

LDC.L @Rm+,GBR ((Rm)GBR, Rm + 4Rm) 0100mmmm00010111

LdcLVbr(SuperHRegister)

LDC.L @Rm+,VBR ((Rm)VBR, Rm + 4Rm) 0100mmmm00100111

Privileged

LdcLSsr(SuperHRegister)

LDC.L @Rm+,SSR ((Rm)SSR, Rm + 4Rm) 0100mmmm00110111

Privileged Level: Sh3

LdcLSpc(SuperHRegister)

LDC.L @Rm+,SPC ((Rm)SPC, Rm + 4Rm) 0100mmmm01000111

Privileged Level: Sh3

LdcLDbr(SuperHRegister)

LDC.L @Rm+,DBR ((Rm)DBR, Rm + 4Rm) 0100mmmm11110110

Privileged Level: Sh4

LdcLRnBank(SuperHRegisterSuperHRegisterBank)

LDC.L @Rm+,Rn_BANK ((Rm)Rn_BANK (n = 0 to 7), Rm + 4Rm) 0100mmmm1nnn0111

Privileged Level: Sh3

LdsMach(SuperHRegister)

LDS Rm,MACH (RmMACH) 0100mmmm00001010

LdsMacl(SuperHRegister)

LDS Rm,MACL (RmMACL) 0100mmmm00011010

LdsPr(SuperHRegister)

LDS Rm,PR (RmPR) 0100mmmm00101010

LdsLMach(SuperHRegister)

LDS.L @Rm+,MACH ((Rm)MACH, Rm + 4Rm) 0100mmmm00000110

LdsLMacl(SuperHRegister)

LDS.L @Rm+,MACL ((Rm)MACL, Rm + 4Rm) 0100mmmm00010110

LdsLPr(SuperHRegister)

LDS.L @Rm+,PR ((Rm)PR, Rm + 4Rm) 0100mmmm00100110

Ldtlb

LDTLB (PTEH/PTELTLB) 0000000000111000

Privileged Features: MMU Level: Sh3

MovcaL(SuperHRegister)

MOVCA.L R0,@Rn (R0(Rn) (without fetchingcache block)) 0000nnnn11000011

Level: Sh4

Nop

NOP (No operation) 0000000000001001

OcbI(SuperHRegister)

OCBI @Rn (Invalidates operand cache block) 0000nnnn10010011

Level: Sh4

OcbP(SuperHRegister)

OCBP @Rn (Writes back and invalidates operand cache block) 0000nnnn10100011

Level: Sh4

OcbWb(SuperHRegister)

OCBWB @Rn (Writes back operand cache block) 0000nnnn10110011

Level: Sh4

Pref(SuperHRegister)

PREF @Rn ((Rn) → operand cache) 0000nnnn10000011

Level: Sh3

Rte

RTE (Delayed branch; SSR/SPCSR/PC) 0000000000101011

Privileged

SetS

SETS (1 → S) 0000000001011000

Level: Sh3

SetT

SETT (1 → T) 0000000000011000 T = 0

Sleep

SLEEP (Sleep or standby) 0000000000011011

Privileged

StcSr(SuperHRegister)

STC SR,Rn (SRRn) 0000nnnn00000010

Privileged

StcGbr(SuperHRegister)

STC GBR,Rn (GBRRn) 0000nnnn00010010

StcVbr(SuperHRegister)

STC VBR,Rn (VBRRn) 0000nnnn00100010

Privileged

StcSsr(SuperHRegister)

STC SSR,Rn (SSRRn) 0000nnnn00110010

Privileged Level: Sh3

StcSpc(SuperHRegister)

STC SPC,Rn (SPCRn) 0000nnnn01000010

Privileged Level: Sh3

StcSgr(SuperHRegister)

STC SGR,Rn (SGRRn) 0000nnnn00111010

Privileged Level: Sh4

StcDbr(SuperHRegister)

STC DBR,Rn (DBRRn) 0000nnnn11111010

Privileged Level: Sh4

StcRmBank(SuperHRegisterBankSuperHRegister)

STC Rm_BANK,Rn (Rm_BANKRn (m = 0 to 7)) 0000nnnn1mmm0010

Privileged Level: Sh3

StcLSr(SuperHRegister)

STC.L SR,@-Rn (Rn - 4Rn, SR(Rn)) 0100nnnn00000011

Privileged

StcLGbr(SuperHRegister)

STC.L GBR,@-Rn (Rn - 4Rn, GBR(Rn)) 0100nnnn00010011

StcLVbr(SuperHRegister)

STC.L VBR,@-Rn (Rn - 4Rn, VBR(Rn)) 0100nnnn00100011

Privileged

StcLSsr(SuperHRegister)

STC.L SSR,@-Rn (Rn - 4Rn, SSR(Rn)) 0100nnnn00110011

Privileged Level: Sh3

StcLSpc(SuperHRegister)

STC.L SPC,@-Rn (Rn - 4Rn, SPC(Rn)) 0100nnnn01000011

Privileged Level: Sh3

StcLSgr(SuperHRegister)

STC.L SGR,@-Rn (Rn - 4Rn, SGR(Rn)) 0100nnnn00110010

Privileged Level: Sh4

StcLDbr(SuperHRegister)

STC.L DBR,@-Rn (Rn - 4Rn, DBR(Rn)) 0100nnnn11110010

Privileged Level: Sh4

StcLRmBank(SuperHRegisterBankSuperHRegister)

STC.L Rm_BANK,@-Rn (Rn - 4Rn, Rm_BANK(Rn) (m = 0 to 7)) 0100nnnn1mmm0011

Privileged Level: Sh3

StsMach(SuperHRegister)

STS MACH,Rn (MACHRn) 0000nnnn00001010

StsMacl(SuperHRegister)

STS MACL,Rn (MACLRn) 0000nnnn00011010

StsPr(SuperHRegister)

STS PR,Rn (PRRn) 0000nnnn00101010

StsLMach(SuperHRegister)

STS.L MACH,@-Rn (Rn - 4Rn, MACH(Rn)) 0100nnnn00000010

StsLMacl(SuperHRegister)

STS.L MACL,@-Rn (Rn - 4Rn, MACL(Rn)) 0100nnnn00010010

StsLPr(SuperHRegister)

STS.L PR,@-Rn (Rn - 4Rn, PR(Rn)) 0100nnnn00100010

Trapa(u8)

TRAPA #imm (PC + 2SPC, SRSSR, #imm << 2TRA, 0x160EXPEVT, VBR + 0x0100PC) 11000011iiiiiiii

Fldi0(SuperHFloatRegister)

FLDI0 FRn (0x00000000FRn) 1111nnnn10001101

Features: FPU Level: Sh4

Fldi1(SuperHFloatRegister)

FLDI1 FRn (0x3F800000FRn) 1111nnnn10011101

Features: FPU Level: Sh4

FMovS(SuperHFloatRegisterSuperHFloatRegister)

FMOV FRm,FRn (FRmFRn) 1111nnnnmmmm1100

Features: FPU Level: Sh4

FMovAtRegS(SuperHRegisterSuperHFloatRegister)

FMOV.S @Rm,FRn ((Rm)FRn) 1111nnnnmmmm1000

Features: FPU Level: Sh4

FMovAtIndexedRegisterS(SuperHRegisterSuperHFloatRegister)

FMOV.S @(R0,Rm),FRn ((R0 + Rm)FRn) 1111nnnnmmmm0110

Features: FPU Level: Sh4

FMovAtPostIncrementRegS(SuperHRegisterSuperHFloatRegister)

FMOV.S @Rm+,FRn ((Rm)FRn, Rm + 4Rm) 1111nnnnmmmm1001

Features: FPU Level: Sh4

FMovToAtRegS(SuperHFloatRegisterSuperHRegister)

FMOV.S FRm,@Rn (FRm(Rn)) 1111nnnnmmmm1010

Features: FPU Level: Sh4

FMovToAtPreDecrementRegS(SuperHFloatRegisterSuperHRegister)

FMOV.S FRm,@-Rn (Rn - 4Rn, FRm(Rn)) 1111nnnnmmmm1011

Features: FPU Level: Sh4

FMovToAtIndexedRegisterS(SuperHFloatRegisterSuperHRegister)

FMOV.S FRm,@(R0,Rn) (FRm(R0 + Rn)) 1111nnnnmmmm0111

Features: FPU Level: Sh4

FMov(SuperHDoubleRegisterSuperHDoubleRegister)

FMOV DRm,DRn (DRmDRn) 1111nnn0mmm01100

Features: FPU Level: Sh4

FMovAtReg(SuperHRegisterSuperHDoubleRegister)

FMOV @Rm,DRn ((Rm)DRn) 1111nnn0mmmm1000

Features: FPU Level: Sh4

FMovAtIndexedRegister(SuperHRegisterSuperHDoubleRegister)

FMOV @(R0,Rm),DRn ((R0 + Rm)DRn) 1111nnn0mmmm0110

Features: FPU Level: Sh4

FMovAtPostIncrementReg(SuperHRegisterSuperHDoubleRegister)

FMOV @Rm+,DRn ((Rm)DRn, Rm + 8Rm) 1111nnn0mmmm1001

Features: FPU Level: Sh4

FMovToAtReg(SuperHDoubleRegisterSuperHRegister)

FMOV DRm,@Rn (DRm(Rn)) 1111nnnnmmm01010

Features: FPU Level: Sh4

FMovToAtPreDecrementReg(SuperHDoubleRegisterSuperHRegister)

FMOV DRm,@-Rn (Rn - 8Rn, DRm(Rn)) 1111nnnnmmm01011

Features: FPU Level: Sh4

FMovToAtIndexedRegister(SuperHDoubleRegisterSuperHRegister)

FMOV DRm,@(R0,Rn) (DRm(R0 + Rn)) 1111nnnnmmm00111

Features: FPU Level: Sh4

Flds(SuperHFloatRegister)

FLDS FRm,FPUL (FRmFPUL) 1111mmmm00011101

Features: FPU Level: Sh4

Fsts(SuperHFloatRegister)

FSTS FPUL,FRn (FPULFRn) 1111nnnn00001101

Features: FPU Level: Sh4

FabsS(SuperHFloatRegister)

FABS FRn (FRn & 0x7FFF_FFFFFRn) 1111nnnn01011101

Features: FPU Level: Sh4

FaddS(SuperHFloatRegisterSuperHFloatRegister)

FADD FRm,FRn (FRn + FRmFRn) 1111nnnnmmmm0000

Features: FPU Level: Sh4

FcmpEqS(SuperHFloatRegisterSuperHFloatRegister)

FCMP/EQ FRm,FRn (When FRn = FRm, 1 → T; Otherwise, 0 → T) 1111nnnnmmmm0100 T = Comparison result

Features: FPU Level: Sh4

FcmpGtS(SuperHFloatRegisterSuperHFloatRegister)

FCMP/GT FRm,FRn (When FRn > FRm, 1 → T; Otherwise, 0 → T) 1111nnnnmmmm0101 T = Comparison result

Features: FPU Level: Sh4

FdivS(SuperHFloatRegisterSuperHFloatRegister)

FDIV FRm,FRn (FRn / FRmFRn) 1111nnnnmmmm0011

Features: FPU Level: Sh4

FloatS(SuperHFloatRegister)

FLOAT FPUL,FRn ((float)FPULFRn) 1111nnnn00101101

Features: FPU Level: Sh4

Fmac(SuperHFloatRegisterSuperHFloatRegister)

FMAC FR0,FRm,FRn (FR0 * FRm + FRnFRn) 1111nnnnmmmm1110

Features: FPU Level: Sh4

FmulS(SuperHFloatRegisterSuperHFloatRegister)

FMUL FRm,FRn (FRn * FRmFRn) 1111nnnnmmmm0010

Features: FPU Level: Sh4

FnegS(SuperHFloatRegister)

FNEG FRn (FRn ^ 0x8000_0000FRn) 1111nnnn01001101

Features: FPU Level: Sh4

FsqrtS(SuperHFloatRegister)

FSQRT FRn (√FRnFRn) 1111nnnn01101101

Features: FPU Level: Sh4

FsubS(SuperHFloatRegisterSuperHFloatRegister)

FSUB FRm,FRn (FRn - FRmFRn) 1111nnnnmmmm0001

Features: FPU Level: Sh4

FrtcS(SuperHFloatRegister)

FRTC FPUL,FRm ((long)FRmFPUL) 1111mmmm00111101

Features: FPU Level: Sh4

Fabs(SuperHDoubleRegister)

FABS DRn (DRn & 0x7FFF_FFFF_FFFF_FFFFDRn) 1111nnn001011101

Features: FPU Level: Sh4

Fadd(SuperHDoubleRegisterSuperHDoubleRegister)

FADD DRm,DRn (DRn + DRmDRn) 1111nnn0mmm00000

Features: FPU Level: Sh4

FcmpEq(SuperHDoubleRegisterSuperHDoubleRegister)

FCMP/EQ DRm,DRn (When DRn = DRm, 1 → T; Otherwise, 0 → T) 1111nnn0mmm00100 T = Comparison result

Features: FPU Level: Sh4

FcmpGt(SuperHDoubleRegisterSuperHDoubleRegister)

FCMP/GT DRm,DRn (When DRn > DRm, 1 → T; Otherwise, 0 → T) 1111nnn0mmm00101 T = Comparison result

Features: FPU Level: Sh4

Fdiv(SuperHDoubleRegisterSuperHDoubleRegister)

FDIV DRm,DRn (DRn / DRmDRn) 1111nnn0mmm00011

Features: FPU Level: Sh4

FcnvDs(SuperHDoubleRegister)

FCNVDS DRm,FPUL (double_to_float[DRm]FPUL) 1111mmm010111101

Features: FPU Level: Sh4

FcnvSd(SuperHDoubleRegister)

FCNVSD FPUL,DRn (float_to_double[FPUL]DRn) 1111nnn010101101

Features: FPU Level: Sh4

Float(SuperHDoubleRegister)

FLOAT FPUL,DRn ((float)FPULDRn) 1111nnn000101101

Features: FPU Level: Sh4

Fmul(SuperHDoubleRegisterSuperHDoubleRegister)

FMUL DRm,DRn (DRn * DRmDRn) 1111nnn0mmm00010

Features: FPU Level: Sh4

Fneg(SuperHDoubleRegister)

FNEG DRn (DRn ^ 0x8000_0000_0000_0000DRn) 1111nnn001001101

Features: FPU Level: Sh4

Fsqrt(SuperHDoubleRegister)

FSQRT DRn (√DRnDRn) 1111nnn001101101

Features: FPU Level: Sh4

Fsub(SuperHDoubleRegisterSuperHDoubleRegister)

FSUB DRm,DRn (DRn - DRmDRn) 1111nnn0mmm00001

Features: FPU Level: Sh4

Frtc(SuperHDoubleRegister)

FRTC FPUL,DRm ((long)DRmFPUL) 1111mmm000111101

Features: FPU Level: Sh4

LdsFpscr(SuperHRegister)

LDS Rm,FPSCR (RmFPSCR) 0100mmmm01101010

Features: FPU Level: Sh4

LdsFpul(SuperHRegister)

LDS Rm,FPUL (RmFPUL) 0100mmmm01011010

Features: FPU Level: Sh4

LdsFpscrL(SuperHRegister)

LDS @Rm+,FPSCR (RmFPSCR, Rm + 4Rm) 0100mmmm01100110

Features: FPU Level: Sh4

LdsFpulL(SuperHRegister)

LDS @Rm+,FPUL (RmFPUL, Rm + 4Rm) 0100mmmm01010110

Features: FPU Level: Sh4

StsFpscr(SuperHRegister)

STS FPSCR,Rn (FPSCRRn) 0000nnnn01101010

Features: FPU Level: Sh4

StsFpul(SuperHRegister)

STS FPUL,Rn (FPULRn) 0000nnnn01011010

Features: FPU Level: Sh4

StsFpscrL(SuperHRegister)

STS FPSCR,@-Rn (Rn - 4Rn, FPSCRRn) 0100nnnn01100010

Features: FPU Level: Sh4

StsFpulL(SuperHRegister)

STS FPUL,@-Rn (Rn - 4Rn, FPULRn) 0100nnnn01010010

Features: FPU Level: Sh4

FMovToX(SuperHDoubleRegisterSuperHExtendedDoubleRegister)

FMOV DRm,XDn (DRmXDn) 1111nnn1mmm01100

Features: FPU Level: Sh4

FMovFromX(SuperHExtendedDoubleRegisterSuperHDoubleRegister)

FMOV XDm,DRn (XDmDRn) 1111nnn0mmm11100

Features: FPU Level: Sh4

FMovX(SuperHExtendedDoubleRegisterSuperHExtendedDoubleRegister)

FMOV XDm,XDn (XDmXDn) 1111nnn1mmm11100

Features: FPU Level: Sh4

FMovAtRegX(SuperHRegisterSuperHExtendedDoubleRegister)

FMOV @Rm,XDn ((Rm)XDn) 1111nnn1mmmm1000

Features: FPU Level: Sh4

FMovAtPostIncrementRegX(SuperHRegisterSuperHExtendedDoubleRegister)

FMOV @Rm+,XDn ((Rm)XDn, Rm + 8Rm) 1111nnn1mmmm1001

Features: FPU Level: Sh4

FMovAtIndexedRegisterX(SuperHRegisterSuperHExtendedDoubleRegister)

FMOV @(R0,Rm),XDn ((R0 + Rm)XDn) 1111nnn1mmmm0110

Features: FPU Level: Sh4

FMovToAtRegX(SuperHExtendedDoubleRegisterSuperHRegister)

FMOV XDm,@Rn (XDm(Rn)) 1111nnnnmmm11010

Features: FPU Level: Sh4

FMovToAtPreDecrementRegX(SuperHExtendedDoubleRegisterSuperHRegister)

FMOV XDm,@-Rn (Rn - 8Rn, XDm(Rn)) 1111nnnnmmm11011

Features: FPU Level: Sh4

FMovToAtIndexedRegisterX(SuperHExtendedDoubleRegisterSuperHRegister)

FMOV XDm,@(R0,Rn) (XDm(R0 + Rn)) 1111nnnnmmm10111

Features: FPU Level: Sh4

Fipr(SuperHVectorFloatRegisterSuperHVectorFloatRegister)

FIPR FVm,FVn (inner_product[FVm, FVn]FR[n + 3]) 1111nnmm11101101

Features: FPU Level: Sh4

Xmrtx(SuperHVectorFloatRegister)

XMRTX FVn (transform_vector[XMTRX, FVn]FVn) 1111nn0111111101

Features: FPU Level: Sh4

FrChg

FRCHG (~FPSCR.FRSPFCR.FR) 1111101111111101

Features: FPU Level: Sh4

FsChg

FSCHG (~FPSCR.SZSPFCR.SZ) 1111001111111101

Features: FPU Level: Sh4

CasL(SuperHRegisterSuperHRegister)

CAS.L Rm,Rn,@R0 (When a byte in Rn equals a byte in Rm, 1 → T) 0010nnnnmmmm0011

https://github.com/j-core/jcore-cpu/blob/00f398e/decode/decode_table_simple.vhd#L1919

Features: J2 Level: J2

Implementations

Parse a single instruction with the specified architectural state

This parses among all valid instructions; feature-gating must be performed separately

Trait Implementations

Returns a copy of the value. Read more
Performs copy-assignment from source. Read more
Formats the value using the given formatter. Read more
Returns the “default value” for a type. Read more
Formats the value using the given formatter. Read more
Feeds this value into the given Hasher. Read more
Feeds a slice of this type into the given Hasher. Read more
Converts this type into the (usually inferred) input type.
the length, in terms of Unit, of this instruction. because Unit will be a diff of an architecture’s Address type, this almost always is a number of bytes. implementations should indicate if this is ever not the case. Read more
the length, in terms of Unit, of the shortest possible instruction in a given architecture.. because Unit will be a diff of an architecture’s Address type, this almost always is a number of bytes. implementations should indicate if this is ever not the case. Read more
This method returns an Ordering between self and other. Read more
Compares and returns the maximum of two values. Read more
Compares and returns the minimum of two values. Read more
Restrict a value to a certain interval. Read more
This method tests for self and other values to be equal, and is used by ==. Read more
This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason. Read more
This method returns an ordering between self and other values if one exists. Read more
This method tests less than (for self and other) and is used by the < operator. Read more
This method tests less than or equal to (for self and other) and is used by the <= operator. Read more
This method tests greater than (for self and other) and is used by the > operator. Read more
This method tests greater than or equal to (for self and other) and is used by the >= operator. Read more

Auto Trait Implementations

Blanket Implementations

Gets the TypeId of self. Read more
Immutably borrows from an owned value. Read more
Mutably borrows from an owned value. Read more

Returns the argument unchanged.

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

The resulting type after obtaining ownership.
Creates owned data from borrowed data, usually by cloning. Read more
Uses borrowed data to replace owned data, usually by cloning. Read more
Converts the given value to a String. Read more
The type returned in the event of a conversion error.
Performs the conversion.
The type returned in the event of a conversion error.
Performs the conversion.